From HLS and RTL to timing closure — with skills built for agent-driven FPGA work. AMD Vivado / Vitis engineering skills · Multi-agent design-space exploration
概要
From HLS and RTL to timing closure — with skills built for agent-driven FPGA work. AMD Vivado / Vitis engineering skills · Multi-agent design-space exploration Quick start · Skill library · Workflows · Agentic-DSE · Resources 1. Pick a skill from the library below, or use DSE-agent for design-space exploration. 2. Use your platform's skill mechanism, or provide its SKILL.md and supporting resources directly. Keep the folder intact and preserve existing installations unless replacing them is part of your request. 3. Specify whether you want analysis, script generation, execution, or optimization. Related skills can work together within the same authorized task. The skills use AMD Vivado/Vitis as their primary baseline. Use the commands and device support available in your installed toolchain. Select the supporting skill for the next required activity; these connections do not require every task to run the full flow.
README
Two ways to work
| Focused FPGA engineering | Multi-agent exploration |
|---|---|
| Nine reusable skills covering HLS, synthesis, constraints, implementation, analysis, timing closure, simulation, TCL, and hardware debug. | A Main Agent coordinates Explorer, Exploiter, and Innovator workers to search architecture, pragma, parameter, and clock choices. |
| Start with: a design, report, script, or engineering question. | Start with: a benchmark, numerical contract, objectives, and a bounded search budget. |
| Browse the skills → | Explore Agentic-DSE → |
Quick start
- Choose an entry point. Pick a skill from the library below, or use DSE-agent for design-space exploration.
- Make the folder available to your agent. Use your platform’s skill mechanism, or provide its
SKILL.mdand supporting resources directly. Keep the folder intact and preserve existing installations unless replacing them is part of your request. - Describe the outcome and boundaries. Specify whether you want analysis, script generation, execution, or optimization. Related skills can work together within the same authorized task.
| Your goal | Example request |
|---|---|
| Understand a report | “Review this timing report and explain the likely bottleneck. Do not change the design.” |
| Prepare automation | “Generate a batch TCL script for the existing project, but do not run it.” |
| Run implementation | “Run the existing implementation flow and verify the requested outputs. Preserve the constraints and do not program hardware.” |
| Improve timing | “Improve timing within the current RTL and clock target, keep the best candidate, and report any remaining acceptance failures.” |
The skills use AMD Vivado/Vitis 2025.2 documentation as their primary baseline. Use the commands and device support available in your installed toolchain.
Skill library
| Skill | What it covers | AMD guides |
|---|---|---|
| vitis-hls-synthesis | C/C++ to RTL, pragmas, interfaces, dataflow, pipelining, burst optimization, and stage-specific checks | UG1399 |
| vivado-synth | Synthesis strategies, resource inference, attributes, FSM encoding, hierarchy, and OOC/incremental synthesis | UG901 |
| vivado-constraints | Clocks, I/O delays, timing exceptions, CDC, physical constraints, and XDC debugging | UG903 |
| vivado-impl | Placement, routing, physical optimization, congestion, incremental implementation, and ECO tactics | UG904 |
| vivado-analysis | Timing paths, QoR, methodology, utilization, diagnosis, and acceptance evidence | UG906 |
| vivado-timing-closure | Constraint baselines, iterative optimization, best-candidate preservation, and final timing acceptance | UG949 · UG1292 · XTP301 |
| vivado-sim | Behavioral/netlist/timing simulation, xsim, third-party simulators, and SAIF/VCD | UG900 |
| vivado-tcl | Script generation and review, authorized batch execution, result verification, and requested outputs | UG835 · UG892 |
| vivado-debug | ILA, VIO, JTAG-to-AXI, debug insertion, clock requirements, and hardware troubleshooting | UG908 |
Engineering workflows
HLS C/C++ → RTL → Synthesis → Implementation → Timing verification
| Along the flow | Skills to use |
|---|---|
| Constraints and report analysis | vivado-constraints + vivado-analysis |
| Iterative timing improvement | vivado-timing-closure + vivado-impl |
| Simulation throughout development | vivado-sim |
| TCL automation across stages | vivado-tcl |
| Hardware debug, when requested and authorized | vivado-debug |
Agentic-DSE
Explore the design space, preserve the evidence, and retain the best candidates.
Agentic-DSE separates orchestration from candidate implementation. Main handles requirements, architecture proposals, assignments, evidence checks, archival, Pareto selection, and learned knowledge.
| Worker | Search behavior | Cold-start behavior |
|---|---|---|
| Explorer | Broad architecture and parameter exploration | Implements a new seed from the benchmark |
| Exploiter | Local refinement of a baseline or validated parent | Establishes or refines the baseline |
| Innovator | Feature-level crossover of compatible parents | Uses an explicit seed or single-parent variant |
Each round uses fresh worker identities and isolated workspaces. Limited concurrency is handled by batching all three roles.
Core capabilities
- Flexible task routing: requirement review, architecture advice, Pareto inspection, and convergence diagnosis can remain read-only.
- Bounded search: fixed-round or until-converged execution, with a finite round limit and one total attempt budget per assignment.
- Two validation modes: formal Csim/Csynth/Cosim/implementation workflows, or explicitly requested cosim-only exploration with separate provisional results.
- Traceable candidates: input fingerprints and stage receipts bind source, headers, test data, configuration, tool identity, and reports.
- Preserved results: immutable candidate archives and parent references survive workspace reuse.
- Comparable metrics: fixed-reference, exact N-dimensional hypervolume records objective units, configuration identity, and separate latency/throughput metrics.
- Private project knowledge: learned knowledge and experiment evidence stay in the selected project, outside the published skill package.
Start a search
Keep the DSE-agent directory intact. Its skill invocation name is $run-agentic-dse. Hosts that load prompts directly can start at SKILL.md or the compatibility agent.md.
-
Select a benchmark. Supply source, testbench/test vectors, target configuration, and objectives or a specification. Both
benchmarks//and legacydesigns//layouts are supported. -
Initialize the project. Ask the agent to prepare the selected benchmark and requirements. Main creates missing state and isolated worker inputs while preserving existing work.
-
Choose the search scope. For example:
- “Run three DSE rounds for this benchmark, preserving its numerical contract.”
- “Run two cosim-only rounds; do not run implementation.”
- “Continue until converged, for at most six rounds.”
- “Show the Pareto front and explain the current bottleneck without changing files.”
These are natural-language requests, not shell commands. Runtime files belong to the selected project, which may be separate from the skill-resource directory.
Resources and setup
FPGA tools. Use your installed Vivado/Vitis toolchain, device licenses, and any required hardware access. Optional helpers such as RapidWright are not bundled; available native tools can still be used for tasks that do not require them.
DSE helpers. Execution uses Python 3.10+ and the configured Vitis CLI. Exact hypervolume uses NumPy and pymoo; status reporting remains available without that optional backend. Multi-agent rounds require an agent host with file access, shell execution, and worker delegation.
Agent hosts. The Markdown instructions are reusable across file-capable hosts. agents/openai.yaml provides optional UI metadata; it does not configure or select a model.
Bundled examples
| Location | Content |
|---|---|
| vivado-synth/examples/ | UG901 RTL templates for RAM, DSP, ROM, SRL, and FSM designs, with companion data files |
| vivado-impl/examples/ug906/ | Three before/after RTL example sets for QoR suggestions |
| vitis-hls-synthesis/examples/ | AMD HLS design, feature, and introductory tutorials |
Support
My Claude account got banned. 😅 If you find this project useful, consider sponsoring me to get a GPT Pro 20× subscription — I’d love to keep building.
License
Licensed under GPL-2.0. Preserve the copyright and license notices in bundled third-party examples.
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