RTL-ASS는 Verilog 및 SystemVerilog 엔지니어링에 대한 Retrieval-first, 공급 업체 중립 코덱 기술입니다. Codex는 RTL 디자인, Testbench, assertion 및 bug-pattern 지식을 측정, 검증된 검증된 액세스를 제공합니다. Codex는 사양, 편집 코드, 적용성, 해석 증거에 대한 이유를 이해하고 최종 구현을 선택합니다.

RTL-ASS는 다른 모델을 호출하지 않으며, Codex의 뒷면 뒤에 RTL을 생성하거나 패치를 적용하거나 사용자 선택 또는 프로젝트 로컬 검증 흐름을 대체합니다. 오픈 소스 EDA 어댑터는 선택적 낙하이며 초급 능력 메커니즘이 없습니다.

측정 된 검색 예에서 RTL-ASS는 modest, Task-specific Efficiency 개선을 보여주었습니다. 관련 서명 폭 지도는 5 쌍의 맞은편에 2.27%에 의해 집계 된 시간을 감소했지만 2 쌍이 빠르고 토큰 사용이 증가했습니다. 별도의 한 쌍 소스 파일 개발 연기 기록 8.61% 적은 탈출 시간 및 21.75% 적은 입력 토큰. 이러한 retrieval 비교의 두 팔은 기술을 사용; 그들은 참조 기여를 측정, 기본 코덱 versus RTL-ASS. 장점은 작업에 따라 다르며 일부 비교 비용이 더 많이 들 수 있습니다.

RTL-ASS 1.3

RTL-ASS is a retrieval-first, vendor-neutral Codex skill for Verilog and SystemVerilog engineering. It gives Codex bounded access to calibrated, provenance-bearing RTL design, testbench, assertion, and bug-pattern knowledge. Codex remains responsible for understanding the specification, editing code, reasoning about applicability, interpreting evidence, and selecting the final implementation.

RTL-ASS does not call another model, generate RTL behind Codex’s back, apply patches, or replace a user-selected or project-local verification flow. Its open-source EDA adapters are optional fallbacks and are never the primary Skill mechanism.

In measured retrieval examples, RTL-ASS showed modest, task-specific efficiency improvements: relevant signed-width guidance reduced aggregate elapsed time by 2.27% across five pairs, although only two pairs were faster and token use increased. A separate one-pair source-file development smoke recorded 8.61% less elapsed time and 21.75% fewer input tokens. Both arms in these retrieval comparisons used the Skill; they measure the reference contribution, not native Codex versus RTL-ASS. Benefits vary by task, and some comparisons cost more. See measured effects and scope, including the source-file smoke’s pending corrected-grader replay.

1.3 capabilities

• Retrieval-first use of explicit SQLite/FTS5 namespaces, immutable receipts, calibrated lifecycle state, provenance, license metadata, RTL/TB/assertion roles, and negative evidence.
• Verilog/SystemVerilog repository inspection without executing source.
• One versioned CompileManifest for ordered sources, library files, include directories, language mode, defines, parameters, and top across every source-based adapter.
• Optional, explicitly selected or confirmed fallbacks for Verilator lint/simulation and Icarus Verilog self-checking simulation evidence.
• Optional, explicitly selected or confirmed Yosys synthesis/bounded SAT, SymbiYosys assertion, and EQY equivalence fallbacks with explicit solver, depth, initialization, and counterexample semantics.
• Optional, explicitly selected or confirmed OpenSTA evidence only from an exact netlist, Liberty library, and SDC; unconstrained endpoints block closure claims.
• Bounded VCD queries and first-divergence analysis; optional confirmed FST conversion through fst2vcd with original and converted hashes.
• Atomic verification/observation workflows, explicit failure attribution, candidate derivation, and portable license-aware knowledge packs.
• A first-party Apache-2.0 starter pack with RTL, TB, assertions, and focused engineering cards.
• A reviewed 1,429-file open-source HDL corpus lock with isolated provenance and lifecycle state; upstream code is not redistributed.
• A six-class paired Codex workflow audit covering RTL generation, repair, RTL/TB attribution, SystemVerilog signed arithmetic, FST localization, and OpenSTA-driven refinement.