ROCmKernelWiki — AMD CDNA Kernel Optimization Knowledge Base

A structured, agent-queryable knowledge base of AMD Instinct GPU kernel optimization for CDNA3 (gfx942 / MI300) and CDNA4 (gfx950 / MI350–MI355X). It is packaged as a Codex CLI skill, remains compatible with Claude Code, and uses the repository root as the skill directory so one git pull updates both tooling and corpus.

ROCmKernelWiki couples architecture-scoped synthesis to merged-PR and primary-source provenance, real-silicon validation, and a maintainer-controlled evidence flywheel. Automation discovers, triages, and proposes evidence in a rolling PR that starts in Draft; maintainers remain responsible for accepting facts and merging changes.

Corpus freshness: the generated data/corpus-manifest.yaml records the last complete baseline PR-harvest cutoff from data/refresh-cutoff.yaml. Incremental refreshes may add selected evidence after that date; data/evolution-state.yaml records each source’s latest discovery position, not a complete corpus through-date. Doc/blog retrieval dates and guide-sync boundaries advance independently. The captured nod-ai AMDGPU guide commit and retrieval date live in its canonical source page. Tool versions remain pinned in data/tool-versions.yaml. gfx950 facts and examples were verified on MI350X, with guide-specific device/LDS checks repeated on MI355X — see below.

Hardware Scope

Raw PR/source material for other architectures is retained for recovery but is excluded from the active skill, default query results, and generated indices.

The headline portability gotcha: gfx942 FP8 (FNUZ) is not bit-compatible with gfx950 FP8 (OCP). See wiki/migration/gfx942-to-gfx950.md.

Validated on real silicon (MI350X and MI355X / gfx950)

Unlike a docs-only wiki, the gfx950 claims here were checked on an actual AMD Instinct MI350X (ROCm 7.2) by compiling, running, and disassembling code — each finding re-run by an adversarial second pass. Full evidence: VERIFICATION.md and data/hardware-verified.yaml.

The 2026-07-20 guide sync additionally ran on MI355X/ROCm 7.1.1: HIP reported 256 CUs, wave64, 32 waves/CU, and 160 KiB LDS; the upstream empirical-LDS harness reproduced 64 banks plus the b32/b64 phase groups. Its b128 classifier was inconclusive and MI300X SSH access was unavailable, both recorded as limits in VERIFICATION.md.