SAR ADC Design Knowledge Base for Agentic IC design - 시스템 수준의 아키텍처에서 트랜지스터 수준의 구현 및 검증.

이 기술 덮개

sar-adc-skills

SAR ADC design knowledge base for agentic IC design — from system-level architecture to transistor-level implementation and verification.

What This Skill Covers

Every module reference includes a “How to Verify” section with Spectre testbench setup, analysis commands, metric extraction, and pass/fail criteria.

Quick Start

Install as a skill for your AI coding agent:

# Symlink into your project's skills directory
ln -s /path/to/sar-adc-skills/sar-adc-skill .claude/skills/sar-adc

The skill activates on SAR ADC design questions — architecture, CDAC switching, comparator noise, bootstrap sampling, async logic, simulation setup, or ENOB analysis.

Repository Layout

sar-adc-skill/
├── SKILL.md              # Skill definition and read-order guide
├── references/           # 11 technical references (111 KB total)
│   ├── core-architecture.md
│   ├── design-and-tradeoffs.md
│   ├── robustness-and-system.md
│   ├── cdac.md
│   ├── comparator.md
│   ├── bootstrap_switch.md
│   ├── sar-logic.md
│   ├── integration.md
│   ├── simulation-and-verification.md
│   ├── ldo.md
│   └── sar-adc-11b-zzs.md
├── assets/va/            # Verilog-A behavioral models (4-bit SAR)
└── evals/                # Evaluation prompts for skill testing

Design Depth

The skill supports the full design chain:

1. Specs to budgets — ENOB target to noise/timing allocation
2. Architecture — fully differential, charge-redistribution CDAC, dynamic comparator, async/sync SAR
3. Circuit implementation — transistor topologies, sizing guidelines, silicon-proven examples
4. Integration — module connectivity, polarity conventions, differential cross-connections
5. Verification — per-block (PSS+Pnoise, THD, DNL/INL, timing) and full-ADC (ENOB, SNDR, SFDR)

Includes a taped-out 11-bit reference design with complete module hierarchy, transistor sizing, and simulation parameters.