Open Agent Skills and MCP tools for SoC design workflows.
Overview
Open Agent Skills and MCP tools for SoC design workflows. Repository: siliconpeasant/soc_agent_skill Install one skill with the cross-agent skills CLI (Agent Skills spec): -g is user-global. Drop it for a project-local install, or pick clients with -a (Codex, Claude Code, Cursor, …). Each skill directory is standalone: (agent contract), plus MCP server, scripts, and tests. There is no per-skill README. Do not treat this repo as a combined SoC build system (soc-build lives elsewhere). Structural top generation: extract ANSI ports, stitch modules, snapshot interfaces, refresh with soc_update . Unchanged ports: snapshot/CSV is enough — do not regenerate a top just to close a stage. MCP: python3 /path/to/soc-integrate/mcp_server.py (stdio). Frontend CRG only: req table → design Excel + PLL report, then Draw.io / Excalidraw trees. It does emit CRG RTL (crg-gen is a different skill). Reset outputs default to SYNC=N (combine in CRG, sync-release at integrate).
README
SoC Agent Skills
Open Agent Skills and MCP tools for SoC design workflows.
Repository: siliconpeasant/soc_agent_skill
Skills
| Skill | Purpose | MCP | Spec |
|---|---|---|---|
soc-integrate |
Generate/refresh a Verilog chip top from submodule ports | Included, stdio | SKILL.md |
crg-design-gen |
Requirement table → CRG design workbooks and clock/reset trees | Included, stdio | SKILL.md |
wavedrom-gen |
Natural language → official WaveDrom JSON5 + SVG/PNG/HTML | Included, stdio | SKILL.md |
Install one skill with the cross-agent skills CLI
(Agent Skills spec):
npx skills add siliconpeasant/soc_agent_skill --skill soc-integrate -g
npx skills add siliconpeasant/soc_agent_skill --skill crg-design-gen -g
npx skills add siliconpeasant/soc_agent_skill --skill wavedrom-gen -g
-g is user-global. Drop it for a project-local install, or pick clients with
-a (Codex, Claude Code, Cursor, …).
Each skill directory is standalone: SKILL.md is the skill (agent contract), plus MCP server, scripts, and tests. There is no per-skill README.
Do not treat this repo as a combined SoC build system (soc-build lives
elsewhere).
soc-integrate
Structural top generation: extract ANSI ports, stitch modules, snapshot
interfaces, refresh with soc_update only when listed submodule ports
change. Unchanged ports: snapshot/CSV is enough — do not regenerate a top
just to close a stage.
pip install mcp
python3 soc-integrate/scripts/soc_integrate.py integrate \
soc-integrate/examples/uart.v soc-integrate/examples/gpio.v \
-n demo_top -o /tmp/demo_top.v \
--map soc-integrate/examples/port_map.json
MCP: python3 /path/to/soc-integrate/mcp_server.py (stdio).
crg-design-gen
Frontend CRG only: req table → design Excel + PLL report, then Draw.io /
Excalidraw trees. It does not emit CRG RTL (crg-gen is a different
skill). Reset outputs default to SYNC=N (combine in CRG, sync-release at
integrate).
pip install pandas openpyxl mcp
python3 crg-design-gen/scripts/design_main.py \
crg-design-gen/examples/input/req_table_complex.xlsx output/
wavedrom-gen
Official [email protected] engine, local render, no API key.
cd wavedrom-gen && npm ci --omit=dev
node scripts/register-mcp.mjs --agent generic
| Example | Preview |
|---|---|
| QSPI 1-4-4 Quad I/O | SVG |
| A_PGM datasheet annotations | SVG |
The same official renderAny engine and all six shipped skins power
validation, SVG, MCP rendering, and offline HTML. PNG is derived from the
canonical SVG with pinned @resvg/resvg-js.
Develop and test
python3 soc-integrate/tests/test_parser.py -v
cd wavedrom-gen && npm ci && cd ..
node .github/scripts/wavedrom-gen-self-test.mjs
The WaveDrom self-test does a real MCP handshake, discovers tools, validates WaveJSON, and renders every supported output.
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Install
npx skillfish add siliconpeasant/soc_agent_skill