一种能够为单个IP生成完整UVM测试平台支架的技能 根据其规范文档（DOCX / PDF / MD）和注册表 （xlsx / csv / md / IP-XACT）。可同时运行于Claude代码和 Codex CLI（通过Codex Claude Code插件/共享技能加载器）—— 7相流水线、支架脚本和评估线束包括 宿主无关性。目标双重人格：

• DV工程师用UVM序列和uvm_test驱动TB。
• 数据工程工程师将TB通过一个薄的tb_api::任务式BFM驱动 无需UVM专业知识。

状态

预测试实现——技能入门点和核心 配备脚手架/评估脚本。内置一等公交车有 APB从属、AHB-Lite（DUT作为从机或DUT作为主控）以及AXI4-Lite （DUT作为从站或DUT作为主站）。任何其他单通道 请求/响应总线（I2C、SPI、Wishbone、自定义寄存器总线， 流式接口）由通用的备份处理：相同 目录布局和模拟流程，推断出总线形状的部分 每个IP由受约束支架子代理从结构化中获得 握手描述和三个内置示例。

gen-tb

A skill that generates a complete UVM testbench scaffold for a single IP from its specification documents (docx / pdf / md) and register table (xlsx / csv / md / IP-XACT). Runs under both Claude Code and Codex CLI (via the Codex Claude Code plugin / shared skill loader) — the 7-phase pipeline, scaffold scripts, and eval harness are host-agnostic. Targets dual personas:

• DV engineers drive the tb with UVM sequences and uvm_tests.
• DE engineers drive the tb through a thin tb_api:: task-style BFM without needing UVM expertise.

Status

Pre-alpha implementation — the skill entry point and the core scaffold/eval scripts are present. Built-in first-class buses are APB-slave, AHB-Lite (DUT-as-slave or DUT-as-master), and AXI4-Lite (DUT-as-slave or DUT-as-master). Any other single-channel request/response bus (I2C, SPI, Wishbone, custom register buses, streaming interfaces) is handled by a generic fallback: the same directory layout and sim flow, with the bus-shaped pieces inferred per-IP by a constrained scaffold sub-agent from a structured handshake description and the three built-in exemplars.

Local regression fixtures exercise all three built-in protocols in both directions, external-VIP reuse for the slave directions, three generic-bus handshake shapes (req_ack, valid_ready, renamed-APB), and AXI4-Lite degraded mode for DUTs that expose full-AXI burst/ID ports but only do single-beat transfers.

Currently in this repo:

evals/fixtures/    # regression fixtures: built-in buses (uart16550, aes128,
                   #   ahb/axi_lite simple), generic-bus shapes, AXI-full degraded
scripts/           # Input discovery, normalization, scaffold, eval helpers
references/        # Progressive-disclosure implementation contracts
SKILL.md           # Skill entry point

Local development notes under docs/ and plan/ are intentionally not tracked. User-facing and skill-facing documentation lives in README.md and references/.

Project layout

gen-tb/
├── SKILL.md               # the skill entry point
├── references/            # progressive-disclosure detail docs
│   ├── directory_layout.md
│   ├── makefile_contract.md
│   ├── top_sv.md          # top/interface wiring
│   ├── apb.md             # APB agent generation rules
│   ├── apb_external_vip.md
│   ├── ahb.md             # AHB-Lite agent generation rules
│   ├── ahb_external_vip.md
│   ├── axi_lite.md        # AXI4-Lite agent generation rules (slave + master + degraded)
│   ├── axi_lite_external_vip.md
│   ├── generic_bus.md     # generic-bus scaffold contract + review checklist
│   ├── sub_agent_generic_scaffold.md  # generic-mode scaffold sub-agent
│   ├── ral_gen.md
│   ├── refm_dpi.md        # C/Python DPI ref model integration
│   ├── tb_api.md          # DE-friendly task BFM
│   ├── rtl_discovery.md   # Phase 1 schema + bus classification