SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre verification. Includes taped-out 11-bit reference.
概览
SAR ADC design knowledge base for agentic IC design — from system-level architecture to transistor-level implementation and verification. Every module reference includes a section with Spectre testbench setup, analysis commands, metric extraction, and pass/fail criteria. Install as a skill for your AI coding agent: The skill activates on SAR ADC design questions — architecture, CDAC switching, comparator noise, bootstrap sampling, async logic, simulation setup, or ENOB analysis. The skill supports the full design chain: 1. — ENOB target to noise/timing allocation 2. — fully differential, charge-redistribution CDAC, dynamic comparator, async/sync SAR 3. — transistor topologies, sizing guidelines, silicon-proven examples 4. — module connectivity, polarity conventions, differential cross-connections 5.
README
以下为原文 README 节选，完整内容请查看原文。
sar-adc-skills
SAR ADC design knowledge base for agentic IC design — from system-level architecture to transistor-level implementation and verification.
What This Skill Covers
| Topic | Reference |
|---|---|
| SAR operation, CDAC-centered architecture, sync vs async | core-architecture.md |
| Design flow, noise budgets, switching schemes, sampling | design-and-tradeoffs.md |
| PVT, metastability, BER, reference path, supply integrity | robustness-and-system.md |
| CDAC: charge redistribution, cap array, DAC switches, differential operation | cdac.md |
| StrongArm comparator: topology, sizing, offset trim, noise | comparator.md |
| Bootstrap switch: gate boosting, Ron flatness, integration with CDAC | bootstrap_switch.md |
| Async SAR logic: latch chain, DCTRL generation, DAC switch mapping | sar-logic.md |
| Top-level integration: module connectivity, signal flow, cross-connections | integration.md |
| Spectre simulation: coherent sampling, strobe, ADCToolbox, per-block verification | simulation-and-verification.md |
| LDO regulator for clean ADC supply | ldo.md |
| Taped-out 11-bit reference design with full module hierarchy and sizing | sar-adc-11b-zzs.md |
Every module reference includes a “How to Verify” section with Spectre testbench setup, analysis commands, metric extraction, and pass/fail criteria.
Quick Start
Install as a skill for your AI coding agent:
# Symlink into your project's skills directory
ln -s /path/to/sar-adc-skills/sar-adc-skill .claude/skills/sar-adc
The skill activates on SAR ADC design questions — architecture, CDAC switching, comparator noise, bootstrap sampling, async logic, simulation setup, or ENOB analysis.
Repository Layout
sar-adc-skill/
├── SKILL.md # Skill definition and read-order guide
├── references/ # 11 technical references (111 KB total)
│ ├── core-architecture.md
│ ├── design-and-tradeoffs.md
│ ├── robustness-and-system.md
│ ├── cdac.md
│ ├── comparator.md
│ ├── bootstrap_switch.md
│ ├── sar-logic.md
│ ├── integration.md
│ ├── simulation-and-verification.md
│ ├── ldo.md
│ └── sar-adc-11b-zzs.md
├── assets/va/ # Verilog-A behavioral models (4-bit SAR)
└── evals/ # Evaluation prompts for skill testing
Design Depth
The skill supports the full design chain:
- Specs to budgets — ENOB target to noise/timing allocation
- Architecture — fully differential, charge-redistribution CDAC, dynamic comparator, async/sync SAR
- Circuit implementation — transistor topologies, sizing guidelines, silicon-proven examples
- Integration — module connectivity, polarity conventions, differential cross-connections
- Verification — per-block (PSS+Pnoise, THD, DNL/INL, timing) and full-ADC (ENOB, SNDR, SFDR)
Includes a taped-out 11-bit reference design with complete module hierarchy, transistor sizing, and simulation parameters.
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安装
npx skillfish add arcadia-1/sar-adc-skills