Korean | 한국어

하드웨어 엔지니어를 위한 대리인 마구.

현재 개발 버전: 0.6.1 (prerelease). 관련 상품 공지사항

AI 조수 (Claude Code, DeepSeek, Kimi Code - 그들 중 하나) 실제로 schematic을 읽으십시오 - 구성 요소, 그물, 핀, 스크린 샷이 아닙니다 - and do real work on it: 보드를 검토, 문제 표시, 편집 당신의 sign-off는, fab 파일을 수출합니다. 옵션 정보 Pro는 우리가 알고 있는 플랫폼입니다 오늘 내부 아웃; KiCad는 다음, 아키텍처가되었습니다 하루에 다 플랫폼.

무엇 그것

** 리뷰** 편집기를 열고, 하나의 명령:

보고서를 얻을: ERC/DRC, 23 디자인 규칙, 어떤 부분 여전히 데이터 시트가 부족하고, 콘크리트에 모든 발견 구성 요소, 핀 및 그물 - 캔버스에 그려진 마커 문제입니다. 실제 보드에서 디자이너가 잡았다는 것을 잡았습니다. missed - bias가없는 전류 감지 회로, 그 종류의 문제. 당신은 netlist에 대한 일치 규칙에 의해 그들을 찾을 수 없습니다; 당신은해야 건축가가가 감각을 함께하는지 확인하십시오. 철도의 경우 전압은 당신의 머리에서만 생활, intent audit]는 그 그물을 목록으로 만듭니다 한 번 묻습니다. 디자인 기반 계약의 응답 땅

boardwise

English | 中文

An agent harness for hardware engineers.

Current development version: 0.6.1 (prerelease). Published packages are in Releases.

It lets an AI assistant (Claude Code, DeepSeek, Kimi Code — any of them) actually read your schematic — components, nets, pins, not screenshots — and do real work on it: review the board, mark the problems, edit with your sign-off, export the fab files. EasyEDA Pro is the platform we know inside-out today; KiCad is next, and the architecture has been multi-platform from day one.

What it does

Review. With the editor open, one command:

boardwise checkup

You get a report: ERC/DRC, 23 design rules, which parts still lack datasheets, and every finding pointing at a concrete component, pin and net — with markers drawn on the canvas where the problems are. On real boards it has caught things the designer had missed — a current-sense circuit with no bias, that kind of problem. You don’t find those by matching rules against a netlist; you have to check whether the architecture makes sense together. When a rail’s voltage lives only in your head, intent audit lists those nets and asks once; the answer lands in a design-intent contract (intent set-rail) and is never asked again. The PCB review stages already landed have flagged real layout defects on real boards — a motor driver’s exposed pad whose copper pour was left as a thermal island on a four-layer FOC driver, that class of problem.

Edit. Find a problem, get a change preview; nothing moves until you approve; afterwards it reads back and re-reviews to confirm the problem is actually gone. Edit kinds today: change a component value, add a missing part, repair a single pin connection, insert an RC/divider subcircuit, move a functional block.

Export. One export-fab writes the whole fab bundle — Gerber, pick-and-place and BOM together. (There is no netlist export command; the netlist is read internally for review, not written out as a file.)

Draw. You state the circuit intent — a divider, an RC low-pass, an LDO; parts, values, which pin joins which net — and the drawing compiler turns it into a sheet a human can read: where parts sit, how wires run, where text goes so it doesn’t sit on a wire. Wrong connectivity, not enough room, a conflict with your locked placement — it refuses rather than hand you a bad drawing. It compiles offline, and it can also land into the open editor itself — placement, pin readback before any wire, save, and a render of the result. Several modules compose onto one page: what is already on the page becomes keep-outs, your locked placements are honoured, every rail gets a flag, and one draw discard takes a landed page back off.

Newer pieces worth knowing:

• Offline geometry render — checkup --file draws each board to canvas-.svg (two views, findings highlighted); it is drawn from the