단일 IP를 위한 완전한 UVM Testbench 비계를 생성하는 기술 명세서 문서 (docx / pdf / md)에서 테이블 등록 (xlsx/csv/md/IP-XACT). 아래에서 실행 Claude Code 과 ** Codex CLI** (Codex Claude Code 플러그인 / 공유 기술 로더) — 7단계 파이프라인, 비계 스크립트, eval 하네스는 호스트-agnostic. Targets 이중 사람:

• DV 엔지니어는 UVM 시퀀스와 TB를 구동한다. [T0]
• **DE 엔지니어 ** 얇은 tb_api:: 작업 스타일 BFM을 통해 tb를 구동 UVM 전문성을 필요로 하지 않고.

상태

**Pre-alpha 구현 ** - 기술 항목 포인트 및 핵심 비계 / eval 스크립트가 존재합니다. 내장 일류 버스 APB-slave, AHB-Lite (DUT-as-slave 또는 DUT-as-master) 및 AXI4-Lite (DUT-as-slave 또는 DUT-as-master). 다른 단일 채널 요청 / 책임 버스 (I2C, SPI, Wishbone, 사용자 정의 등록 버스, 스트리밍 인터페이스)는 일반적인 fallback에 의해 처리됩니다. 디렉토리 레이아웃 및 sim 흐름, 버스 모양의 조각 inferred 구조상에서 constrained 비계 sub-agent에 의하여 per-IP 손으로 설명과 세 개의 내장 exemplars.

gen-tb

A skill that generates a complete UVM testbench scaffold for a single IP from its specification documents (docx / pdf / md) and register table (xlsx / csv / md / IP-XACT). Runs under both Claude Code and Codex CLI (via the Codex Claude Code plugin / shared skill loader) — the 7-phase pipeline, scaffold scripts, and eval harness are host-agnostic. Targets dual personas:

• DV engineers drive the tb with UVM sequences and uvm_tests.
• DE engineers drive the tb through a thin tb_api:: task-style BFM without needing UVM expertise.

Status

Pre-alpha implementation — the skill entry point and the core scaffold/eval scripts are present. Built-in first-class buses are APB-slave, AHB-Lite (DUT-as-slave or DUT-as-master), and AXI4-Lite (DUT-as-slave or DUT-as-master). Any other single-channel request/response bus (I2C, SPI, Wishbone, custom register buses, streaming interfaces) is handled by a generic fallback: the same directory layout and sim flow, with the bus-shaped pieces inferred per-IP by a constrained scaffold sub-agent from a structured handshake description and the three built-in exemplars.

Local regression fixtures exercise all three built-in protocols in both directions, external-VIP reuse for the slave directions, three generic-bus handshake shapes (req_ack, valid_ready, renamed-APB), and AXI4-Lite degraded mode for DUTs that expose full-AXI burst/ID ports but only do single-beat transfers.

Currently in this repo:

evals/fixtures/    # regression fixtures: built-in buses (uart16550, aes128,
                   #   ahb/axi_lite simple), generic-bus shapes, AXI-full degraded
scripts/           # Input discovery, normalization, scaffold, eval helpers
references/        # Progressive-disclosure implementation contracts
SKILL.md           # Skill entry point

Local development notes under docs/ and plan/ are intentionally not tracked. User-facing and skill-facing documentation lives in README.md and references/.

Project layout

gen-tb/
├── SKILL.md               # the skill entry point
├── references/            # progressive-disclosure detail docs
│   ├── directory_layout.md
│   ├── makefile_contract.md
│   ├── top_sv.md          # top/interface wiring
│   ├── apb.md             # APB agent generation rules
│   ├── apb_external_vip.md
│   ├── ahb.md             # AHB-Lite agent generation rules
│   ├── ahb_external_vip.md
│   ├── axi_lite.md        # AXI4-Lite agent generation rules (slave + master + degraded)
│   ├── axi_lite_external_vip.md
│   ├── generic_bus.md     # generic-bus scaffold contract + review checklist
│   ├── sub_agent_generic_scaffold.md  # generic-mode scaffold sub-agent
│   ├── ral_gen.md
│   ├── refm_dpi.md        # C/Python DPI ref model integration
│   ├── tb_api.md          # DE-friendly task BFM
│   ├── rtl_discovery.md   # Phase 1 schema + bus classification