논문 구현: MCP4EDA: LLM 기반 모델 컨텍스트 프로토콜 RTL-to-GDSII 자동화와 백엔드 인식 합성 최적화

Claude Desktop 및 Cursor IDE와 같은 AI 어시스턴트에 전자 설계 자동화(EDA) 도구 통합을 제공하는 종합적인 모델 컨텍스트 프로토콜(MCP) 서버입니다. 이 서버는 통합 인터페이스를 통해 AI가 Verilog 합성, 시뮬레이션, ASIC 설계 흐름 및 파형 분석을 수행할 수 있도록 합니다.

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데모

https://github.com/user-attachments/assets/65d8027e-7366-49b5-8f11-0430c1d1d3d6

EDA MCP 서버 시연, Verilog 합성, 시뮬레이션 및 ASIC 설계 흐름

특징

• Verilog Synthesis: Yosys를 사용하여 다양한 FPGA 대상(일반, ice40, xilinx)에 대해 Verilog 코드를 합성합니다.
• Verilog 시뮬레이션: Icarus Verilog를 사용해 자동 테스트벤치 실행을 이용한 설계 시뮬레이션
• 파형 뷰잉: VCD 파일 시각화 및 신호 분석을 위해 GTKWave 실행
• ASIC 설계 흐름: OpenLane과 Docker 통합을 이용한 완전한 RTL에서 GDSII 프로세스
• 레이아웃 보기: KLayout에서 GDSII 파일을 열어 물리적 설계 검사를 위해

EDA Tools MCP Server

Implementation of the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

A comprehensive Model Context Protocol (MCP) server that provides Electronic Design Automation (EDA) tools integration for AI assistants like Claude Desktop and Cursor IDE. This server enables AI to perform Verilog synthesis, simulation, ASIC design flows, and waveform analysis through a unified interface.

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Demo

https://github.com/user-attachments/assets/65d8027e-7366-49b5-8f11-0430c1d1d3d6

EDA MCP Server demonstration showing Verilog synthesis, simulation, and ASIC design flow

Features

• Verilog Synthesis: Synthesize Verilog code using Yosys for various FPGA targets (generic, ice40, xilinx)
• Verilog Simulation: Simulate designs using Icarus Verilog with automated testbench execution
• Waveform Viewing: Launch GTKWave for VCD file visualization and signal analysis
• ASIC Design Flow: Complete RTL-to-GDSII flow using OpenLane with Docker integration
• Layout Viewing: Open GDSII files in KLayout for physical design inspection
• Report Analysis: Read and analyze OpenLane reports for PPA metrics and design quality assessment

Prerequisites

Before using this MCP server, you need to install the following EDA tools:

1. Yosys (Verilog Synthesis)

macOS (Homebrew):

brew install yosys

Ubuntu/Debian:

sudo apt-get update
sudo apt-get install yosys

From Source:

# Install prerequisites
sudo apt-get install build-essential clang bison flex \
    libreadline-dev gawk tcl-dev libffi-dev git \
    graphviz xdot pkg-config python3 libboost-system-dev \
    libboost-python-dev libboost-filesystem-dev zlib1g-dev

# Clone and build
git clone https://github.com/YosysHQ/yosys.git
cd yosys
make -j$(nproc)
sudo make install

Alternative - OSS CAD Suite (Recommended): Download the complete toolchain from: https://github.com/YosysHQ/oss-cad-suite-build/releases

2. Icarus Verilog (Simulation)

macOS (Homebrew):

brew install icarus-verilog

Ubuntu/Debian:

sudo apt-get install iverilog

Windows: Download installer from: https://bleyer.org/icarus/

3. GTKWave (Waveform Viewer)

Direct Downloads (Recommended):

• Windows: Download from SourceForge
• macOS: Download from SourceForge or use Homebrew: brew install --cask gtkwave
• Linux: Download from SourceForge or use package manager: sudo apt-get install gtkwave

Alternative Installation Methods:

# macOS (Homebrew)
brew install --cask gtkwave

# Ubuntu/Debian
sudo apt-get install gtkwave

# Build from source (all platforms)
git clone https://github.com/gtkwave/gtkwave.git